Non-volatile semiconductor memory device and method of fabricati

Details Non-volatile semiconductor memory device and method of fabricati Non-volatile semiconductor memory device and method of fabricati

1997-05-21

1998-08-11

Fahmy, Wael

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257316, H01L 2976, H01L 29788

Patent

active

057930783

ABSTRACT:
According to the present invention, there is provided a non-volatile semiconductor memory device including a memory cell array in which a plurality of memory cells are arranged, wherein the memory cells contain two or more types of memory cells, which differs in gate couple ratio. Each memory cell includes source-drain regions provided apart from each other in a semiconductor substrate having a conductivity type, the source-drain regions having a conductivity type opposite to that of the semiconductor substrate, a floating gate provided above a channel region formed between the source-drain regions, and a control gate provided above a surface of the floating gate, and the memory cells contain two or more types of memory cells, which differ in relation to an area of a region in which the floating gate and the control gate overlap. The memory cells having a low gate couple ratio exhibit characteristics similar to those of a mask ROM, which gives priority to reading, whereas the memory cells having a high gate couple ratio, exhibit excellent programming and erasing characteristics.

REFERENCES:
patent: 4223394 (1980-09-01), Pathak et al.
patent: 4811291 (1989-03-01), de Ferron
patent: 4833514 (1989-05-01), Esquivel et al.
patent: 5068697 (1991-11-01), Noda et al.
patent: 5142496 (1992-08-01), Van Buskirk
patent: 5157626 (1992-10-01), Watanabe
patent: 5163021 (1992-11-01), Mehrotra et al.
patent: 5311466 (1994-05-01), Natale et al.
patent: 5349558 (1994-09-01), Cleveland et al.
patent: 5463587 (1995-10-01), Maruyama
patent: 5465231 (1995-11-01), Ohsaki
patent: 5545906 (1996-08-01), Ogura et al.
patent: 5568418 (1996-10-01), Crisenza et al.
Seiji Yamada et al., "A Self-Convergence Erasing Scheme for a Simple Stacked Gate Flash EEPROM", IEEE, vol. 11, No. 4, pp. 1-4, 1991.

Affiliated with

Also associated with

Rating

Non-volatile semiconductor memory device and method of fabricati does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Non-volatile semiconductor memory device and method of fabricati, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Non-volatile semiconductor memory device and method of fabricati will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-391739