Semiconductor integrated circuit and leak current reducing...

Details Semiconductor integrated circuit and leak current reducing... Semiconductor integrated circuit and leak current reducing...

2008-09-02

2008-09-02

Le, Vu A (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S229000

Reexamination Certificate

active

11546955

ABSTRACT:
The present invention provides a semiconductor integrated circuit device which includes at least an SRAM memory cell array comprising a plurality of memory cells each constituted of a circuit including load MOS transistors, drive MOS transistors and transfer MOS transistors, a substrate bias generating circuit which is electrically connected to the load MOS transistors and supplies a substrate potential to the load MOS transistors during at least operation and standby, and a source bias generating circuit which is electrically connected to the drive MOS transistors and supplies a source potential to the drive MOS transistors at standby. It is possible to reduce a leak current in an SRAM memory cell during both operation and standby and reduce current consumption.

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