Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Bus or line termination
Reexamination Certificate
2008-05-20
2008-05-20
Tran, Anh Q (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Bus or line termination
C326S033000, C326S026000, C326S027000
Reexamination Certificate
active
11449202
ABSTRACT:
Methods of compensating for power supply variations in an integrated circuit. During operation of the IC die, a power supply voltage level is monitored. When the power supply voltage level drops below a specified level, a performance compensation circuit in the IC is enabled, bringing a first delay (e.g., the rising delay) for a compensated circuit in the IC more closely into alignment with a second delay (e.g., a falling delay) for the circuit. When the power supply voltage level exceeds the specified level, the performance compensation circuit is disabled. When the IC is a programmable IC, for example, the compensated circuit can be a programmable interconnect multiplexer of the programmable IC. In these embodiments, the power supply voltage level for the pass transistors in the interconnect multiplexer can be monitored and compensated for as described above.
REFERENCES:
patent: 5589783 (1996-12-01), McClure
patent: 6177819 (2001-01-01), Nguyen
patent: 6236231 (2001-05-01), Nguyen et al.
patent: 6476638 (2002-11-01), Zhou et al.
patent: 7020764 (2006-03-01), Kubota et al.
patent: 7064582 (2006-06-01), Gallo et al.
patent: 7215150 (2007-05-01), Torres et al.
patent: 7227390 (2007-06-01), Bapat et al.
patent: 7248083 (2007-07-01), Chung
patent: 2004/0113654 (2004-06-01), Lundberg
patent: 2006/0119384 (2006-06-01), Camarota et al.
patent: 2007/0040577 (2007-02-01), Lewis et al.
U.S. Appl. No. 11/449,172, filed Jun. 8, 2006, Schultz.
U.S. Appl. No. 11/449,198, filed Jun. 8, 2006, Rahman.
U.S. Appl. No. 11/449,203, filed Jun. 8, 2006, Rahman.
U.S. Appl. No. 11/449,240, filed Jun. 8, 2006, Schultz.
Arifur Rahman et al.; “Heterogeneous Routing Architecture for Low-Power FPGA Fabric”; IEEE 2005 Custom Integrated Circuits Conference; Copyright 2005 IEEE; pp. 183-186, no month.
Cartier Lois D.
Tran Anh Q
Xilinx , Inc.
LandOfFree
Methods of providing performance compensation for supply... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Methods of providing performance compensation for supply..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Methods of providing performance compensation for supply... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3912573