Method for calibrating a driver and on-die termination of a...

Details Method for calibrating a driver and on-die termination of a... Method for calibrating a driver and on-die termination of a...

2008-07-15

2008-07-15

Cho, James H (Department: 2819)

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Bus or line termination

C326S031000

Reexamination Certificate

active

11638815

ABSTRACT:
An improved driver and ODT impedance calibration techniques of a synchronous memory device are provided. The impedance calibration is performed by generating a calibration enable signal showing a calibration operation mode entry. The code signals for an ODT calibration are generated for every predetermined interval of time. A first control signal is generated based on the calibration enable signal. A final code signal of the sequentially generated code signals is latched by the first control signal to use as a driver and ODT impedance calibration signal.

REFERENCES:
patent: 6166563 (2000-12-01), Volk et al.
patent: 6762620 (2004-07-01), Jang et al.
patent: 7292953 (2007-11-01), Jung
patent: 1020050012931 (2005-02-01), None

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