Semiconductor apparatus and MIS logic circuit

Details Semiconductor apparatus and MIS logic circuit Semiconductor apparatus and MIS logic circuit

2008-09-30

2008-09-30

Elms, Richard T. (Department: 2824)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S347000, C257S348000, C257S296000

Reexamination Certificate

active

11353075

ABSTRACT:
A configuration is adopted including an NchMOS transistor (1) equipped with an insulating isolation layer (4) providing insulation and isolation using an SOI structure, and a capacitor formed using an insulating film, with a silicon substrate (B) being made thin and substrate capacitance being reduced. The NchMOS transistor (1) is equipped with insulating isolation regions (5a,5b) that are perfectly depleted or partially depleted in a manner close to being perfectly depleted. An electrode (6) connected to a gate electrode (G) of the NchMOS transistor (1) and an impurity diffusion layer (7) are connected via a capacitor (2). A source electrode (S) is connected to a power supply terminal (3a), a gate electrode (G) is connected to an internal signal line (S1), and a drain electrode (D) is connected to an internal signal line (S2). Substrate bias voltage is then controlled using capacitor coupling when the NchMOS transistor (1) is turned on/off.

REFERENCES:
patent: 6063686 (2000-05-01), Masuda et al.
patent: 6213869 (2001-04-01), Yu et al.
patent: 6670679 (2003-12-01), Hirata
patent: 7-211079 (1995-08-01), None
patent: 10-242839 (1998-09-01), None
patent: 11-307652 (1999-11-01), None
English Language Abstract of JP7-211079.
English Language Abstract of JP 11-307652.
English Language Abstract of JP 10-242839.

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