Top drain MOSFET

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257S330000, C257S331000, C257S329000, C257S333000, C257S341000, C257S342000, C257S510000

Reexamination Certificate

active

11042993

ABSTRACT:
A power MOSFET is disclosed in which the source and drain regions are reversed from their usual positions and the drain is on the top of the chip (the surface containing the junction pattern diffusions) and the source is on the bottom of the chip. A plurality of spaced trenches are formed in the top surface. One group of trenches contain gate polysilicon and a gate oxide to control an invertible channel region along the trench. A second group of the trenches have a buried source contact at their bottoms which are connected between the N source material to the P channel region to short out a parasitic bipolar transistor.

REFERENCES:
patent: 5134448 (1992-07-01), Johnsen et al.
patent: 6436770 (2002-08-01), Leung et al.

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