Electrical computers and digital processing systems: support – Computer power control – Power conservation
Reexamination Certificate
2008-07-29
2008-07-29
Cao, Chun (Department: 2115)
Electrical computers and digital processing systems: support
Computer power control
Power conservation
C713S323000, C712S234000
Reexamination Certificate
active
11003772
ABSTRACT:
In a pipelined processor, a pre-decoder in advance of an instruction cache calculates the branch target address (BTA) of PC-relative and absolute address branch instructions. The pre-decoder compares the BTA with the branch instruction address (BIA) to determine whether the target and instruction are in the same memory page. A branch target same page (BTSP) bit indicating this is written to the cache and associated with the instruction. When the branch is executed and evaluated as taken, a TLB access to check permission attributes for the BTA is suppressed if the BTA is in the same page as the BIA, as indicated by the BTSP bit. This reduces power consumption as the TLB access is suppressed and the BTA/BIA comparison is only performed once, when the branch instruction is first fetched. Additionally, the pre-decoder removes the BTA/BIA comparison from the BTA generation and selection critical path.
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Dieffenderfer James Norris
Sartorius Thomas Andrew
Smith Rodney Wayne
Stempel Brian Michael
Cao Chun
Ciccozzi John L.
Pauley Nicholas J.
QUALCOMM Incorporated
Rouse Thomas
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