Strained complementary metal oxide semiconductor (CMOS) on...

Active solid-state devices (e.g. – transistors – solid-state diode – Gate arrays – Having specific type of active device

Reexamination Certificate

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C257S274000, C257S628000, C257SE27062, C257SE29139

Reexamination Certificate

active

11112820

ABSTRACT:
The present invention provides CMOS structures including at least one strained pFET that is located on a rotated semiconductor substrate to improve the device performance. Specifically, the present invention utilizes a Si-containing semiconductor substrate having a (100) crystal orientation in which the substrate is rotated by about 45° such that the CMOS device channels are located along the <100> direction. Strain can be induced upon the CMOS structure including at least a pFET and optionally an nFET, particularly the channels, by forming a stressed liner about the FET, by forming embedded stressed wells in the substrate, or by utilizing a combination of embedded stressed wells and a stressed liner. The present invention also provides methods for fabricating the aforesaid semiconductor structures.

REFERENCES:
patent: 5729045 (1998-03-01), Buynoski
patent: 6998684 (2006-02-01), Anderson et al.
patent: 2004/0217448 (2004-11-01), Kumagai et al.
patent: 2004/0256614 (2004-12-01), Ouyang et al.
patent: 2006/0145264 (2006-07-01), Chidambarrao et al.
patent: 2006/0202277 (2006-09-01), Hierlemann et al.
Matsumoto, T. et al. Novel SOI Wafer Engineering Using Low Stress and High Mobility CMOSFET with <100>-Channel for Embedded RF/Analog Applications, IEDM, p. 663, 2002.
Okagaki, T. et al. Direct Measurement of Stress Dependent Inversion Layer Mobility Using a Novel Test Structure, IEEE Symposium on VLSI Technology, p. 120, 2004.
Komoda, T. et al. Mobility Improvement for 45nm Node by Combination of Optimized Stress Control and Channel Orientation Design, IEEE, 2004.

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