Time slot memory management in a switch having back end...

Details Time slot memory management in a switch having back end... Time slot memory management in a switch having back end...

2008-04-01

2008-04-01

Luu, Le Hien (Department: 2141)

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output data buffering

C710S052000

Reexamination Certificate

active

10658900

ABSTRACT:
A switch comprising front-end and back-end application specific integrated circuits (ASICs) is disclosed. Frame storage and retrieval in the switch is achieved by dividing a frame into equal sized portions that are sequentially stored in switch memory during an assigned time slot. Control logic coupled to the front-end and back-end ASICs assigns the time slot either dynamically or statically.

REFERENCES:
patent: 6917614 (2005-07-01), Laubach et al.
patent: 6983414 (2006-01-01), Duschatko et al.
patent: 7181485 (2007-02-01), Lau et al.
patent: 2002/0101860 (2002-08-01), Thornton et al.
patent: 2002/0154646 (2002-10-01), Dubois et al.

Affiliated with

Also associated with

Rating

Time slot memory management in a switch having back end... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Time slot memory management in a switch having back end..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Time slot memory management in a switch having back end... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3904200