Non-volatile two-transistor programmable logic cell and...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S317000, C257S321000

Reexamination Certificate

active

11155005

ABSTRACT:
A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

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patent: 5587603 (1996-12-01), Kowshik
patent: 5625211 (1997-04-01), Kowshik
patent: 5640344 (1997-06-01), Pani et al.
patent: 5740106 (1998-04-01), Nazarian
patent: 5847993 (1998-12-01), Dejenfelt
patent: 6144580 (2000-11-01), Murray
patent: 6252273 (2001-06-01), Salter, III et al.
patent: 6356478 (2002-03-01), McCollum
patent: 2004/0114436 (2004-06-01), Hecht et al.
patent: 2004/0233736 (2004-11-01), Auricchio et al.

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