Static information storage and retrieval – Read/write circuit
Reexamination Certificate
2007-10-09
2007-10-09
Phung, Anh (Department: 2824)
Static information storage and retrieval
Read/write circuit
C365S189050, C365S189080, C365S189110
Reexamination Certificate
active
11542702
ABSTRACT:
A DRAM device includes a mode register that is programmed to select one of two modes for operating data bus terminals in the device. A timing circuit generates timing signals in synchronism with the clock signal that correspond to the selected mode. The timing signals are combined with read data signals to generate corresponding timed read data signals. These timed data signals and termination signals from the timing circuit are applied to pull-up and pull-down circuitry, which drive respective pull-up and pull-down transistors coupled to the data bus terminals. The transistors drive the data bus terminals to either a first or a second voltage if the first mode of operation is selected and to either a third or a fourth voltage if the second mode of operation is selected. Additionally, the pull-up and pull-down transistors bias the data bus terminals to respective voltages corresponding to the selected operating mode.
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Janzen Jeffrey W.
Morzano Christopher
Dorsey & Whitney LLP
Le Toan
Micro)n Technology, Inc.
Phung Anh
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