Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
2007-10-02
2007-10-02
Nguyen, Tan T. (Department: 2827)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S201000
Reexamination Certificate
active
11309782
ABSTRACT:
A downgraded memory module has downgraded DRAM chips soldered to its substrate. The downgraded DRAM chips have a defective memory cell in a logical quadrant of the memory. A physical MSB is a row address present on a non-downgraded DRAM of size S but not used on a downgraded DRAM size S/2. The physical MSB and a second address pin are non-multiplexed address pins that do not carry column addresses. The physical MSB and the second address pin logically divided the DRAM into quadrants. Two good quadrants without defects are selected, and jumpers on the memory module drive the physical MSB and the second address pin with signals that select only these two quadrants and disable access to quadrants containing defects. DRAM chips can be marked or sorted into bins for combinations of good quadrants. Downgraded memory modules have all DRAM chips from the same bin that share jumper settings.
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Chen Mike
Co Ramon S.
Sun David
Auvinen Stuart T.
gPatent LLC
Kingston Technology Corp.
Nguyen Tan T.
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