High wireability microvia substrate

Details High wireability microvia substrate High wireability microvia substrate

2007-10-09

2007-10-09

Ho, Tu-Tu (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Flip chip

C257S691000, C257S776000, C257SE23153

Reexamination Certificate

active

11233572

ABSTRACT:
The escape of signals from a semiconductor chip to a printed wiring board in a flip chip/ball grid array assembly is improved by repositioning the signals from the chip through the upper signal layers of the carrier. This involves fanning out the circuit lines through the chip carrier from the top surface that communicates with the chip through the core to the bottom surface where signals exit the carrier to the printed wiring board, which is achieved by making better utilization of the surface area of the signal planes between the core and the chip. The signals are fanned out on each of the top signal planes so that many more of the signals are transmitted through the vias in the core to the bottom signal planes where they can escape outside of the footprint area of the chip, thereby increasing the density of circuits escaping the footprint area.

REFERENCES:
patent: 4016463 (1977-04-01), Beall et al.
patent: 5095407 (1992-03-01), Kanezawa et al.
patent: 5834705 (1998-11-01), Jonaidi
patent: 6348400 (2002-02-01), Schoenfeld
patent: 6459161 (2002-10-01), Hirata et al.
patent: 2002/0050402 (2002-05-01), Japp et al.
patent: 2003/0094685 (2003-05-01), Shiraishi et al.
patent: 2004/0183171 (2004-09-01), Breisch et al.
patent: 2006/0012054 (2006-01-01), Memis

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