Logic circuit, system for reducing a clock skew, and method...

Details Logic circuit, system for reducing a clock skew, and method... Logic circuit, system for reducing a clock skew, and method...

2007-12-18

2007-12-18

Le, Don (Department: 2819)

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

C326S038000

Reexamination Certificate

active

11068748

ABSTRACT:
A logic circuit includes a first flip-flop configured to include a first input terminal introducing a clock, a first output terminal supplying the clock and a first internal wiring connecting the first input terminal and the first output terminal, and a second flip-flop configured to be adjacent to the first flip-flop and be supplied with the clock from the first output terminal.

REFERENCES:
patent: 5862373 (1999-01-01), Pathikonda et al.
patent: 6053950 (2000-04-01), Shinagawa
patent: 6459310 (2002-10-01), Thomson et al.
patent: 6559701 (2003-05-01), Dillon
patent: 2004/0128579 (2004-07-01), Khondker et al.
patent: 11-272353 (1999-10-01), None
patent: 2000-348083 (2000-12-01), None
patent: 2001-022816 (2001-01-01), None

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