Method and apparatus of evaluating layer matching deviation...

Details Method and apparatus of evaluating layer matching deviation... Method and apparatus of evaluating layer matching deviation...

2007-08-14

2007-08-14

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

10823104

ABSTRACT:
An apparatus of evaluating a layer matching deviation based on CAD information of the invention, is provided with means for storing CAD data and a function of displaying to overlap a scanning microscope image of a pattern of a semiconductor device formed on a wafer and a design CAD image read from the storing means and a function of evaluating acceptability of formation of the pattern by displaying to overlap a pattern image of the semiconductor device formed on the wafer and the design CAD image of the pattern, in addition thereto, a function capable of evaluating acceptability of formation of the pattern also with regard to a shape and positional relationship with a pattern formed at a later step by displaying to overlap a design CAD image of the pattern formed at the later step.

REFERENCES:
patent: 5530372 (1996-06-01), Lee et al.
patent: 6078738 (2000-06-01), Garza et al.
patent: 6493867 (2002-12-01), Mei et al.
patent: 6562638 (2003-05-01), Balasinski et al.
patent: 6757875 (2004-06-01), Matsuoka

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