Integrated semiconductor memory device with test circuit for...

Details Integrated semiconductor memory device with test circuit for... Integrated semiconductor memory device with test circuit for...

2007-10-23

2007-10-23

Phung, Anh (Department: 2824)

Static information storage and retrieval

Read/write circuit

Differential sensing

C365S201000

Reexamination Certificate

active

11324801

ABSTRACT:
An integrated semiconductor memory device includes sense amplifiers that are connected to in each case one bit line pair via controllable voltage generators. In a test mode state, precharging voltages can be fed to at least one of the bit lines of each one of the bit line pairs via the controllable voltage generators. The level of the precharging voltage is dependent on a data item present at a data terminal. The precharging voltages of a bit line pair can be transferred to an adjacent bit line pair via a coupling unit. In a subsequent evaluation process, the prepared precharging voltages are evaluated by the connected sense amplifier.

REFERENCES:
patent: 5184326 (1993-02-01), Hoffman et al.
patent: 5986913 (1999-11-01), Childers et al.
patent: 6301173 (2001-10-01), Fujioka et al.
patent: 6343038 (2002-01-01), Makino et al.
patent: 7120071 (2006-10-01), An

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