System and method for real time optimization of iterative...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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C714S755000

Reexamination Certificate

active

10667700

ABSTRACT:
A system for controlling the number of iterations to be performed by an iterative decoder. The system includes an input port configured to receive a data throughput value, a processor configured to determine an efficient number of iterations for an iterative decoder based on the data throughput value, and an output port configured to provide the efficient number of iterations based on the determination by the processor.

REFERENCES:
patent: 6182261 (2001-01-01), Haller et al.
patent: 6233709 (2001-05-01), Zhang et al.

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