Stacked die memory depth expansion

Details Stacked die memory depth expansion Stacked die memory depth expansion

2007-02-06

2007-02-06

Tran, Michael (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S230030

Reexamination Certificate

active

10996018

ABSTRACT:
Systems and methods for stacked die memory depth expansion. In accordance with a first embodiment of the present invention, a circuit comprises a first memory input enabling depth expansion in a memory. The circuit further comprises a second memory input enabling address range selection in a memory and a plurality of address inputs accessing an expanded memory depth. The circuit also comprises one or more external chip enable inputs and a decoding logic coupled to the first memory input, second memory input, plurality of address inputs and the external chip enable input, wherein the decoding logic generates an internal chip enable signal and a stacked die select signal.

REFERENCES:
patent: 5265063 (1993-11-01), Kogure
patent: 5334875 (1994-08-01), Sugano et al.

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