Semiconductor device and manufacturing method thereof

Details Semiconductor device and manufacturing method thereof Semiconductor device and manufacturing method thereof

2007-02-13

2007-02-13

Schillinger, Laura M. (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S151000, C438S160000

Reexamination Certificate

active

10756455

ABSTRACT:
The present invention provides a semiconductor device in which a bottom-gate TFT or an inverted stagger TFT arranged in each circuit is suitably constructed in conformity with the functionality of the respective circuits, thereby attaining an improvement in the operating efficiency and reliability of the semiconductor device. In the structure, LDD regions in a pixel TFT are arranged so as not to overlap with a channel protection insulating film and to overlap with a gate electrode by at least a portion thereof. LDD regions in an N-channel TFT of a drive circuit is arranged so as not to overlap with a channel protection insulating film and to overlap with a gate electrode by at least a portion thereof. LDD regions in a P-channel TFT of the drive circuit is arranged so as to overlap with a channel protection insulating film and to overlap with the gate electrode.

REFERENCES:
patent: 5292675 (1994-03-01), Codama
patent: 5323042 (1994-06-01), Matsumoto
patent: 5643826 (1997-07-01), Ohtani et al.
patent: 5739065 (1998-04-01), Lin
patent: 5923962 (1999-07-01), Ohtani et al.
patent: 6091115 (2000-07-01), Ohtani et al.
patent: 6096581 (2000-08-01), Zhang et al.
patent: 6166397 (2000-12-01), Yamazaki et al.
patent: 6166414 (2000-12-01), Miyazaki et al.
patent: 6198133 (2001-03-01), Yamazaki et al.
patent: 6218678 (2001-04-01), Zhang et al.
patent: 6259120 (2001-07-01), Zhang et al.
patent: 6271543 (2001-08-01), Ohtani et al.
patent: 6281552 (2001-08-01), Kawasaki et al.
patent: 6346730 (2002-02-01), Kitakado et al.
patent: 6362507 (2002-03-01), Ogawa et al.
patent: 6380007 (2002-04-01), Koyama
patent: 6410368 (2002-06-01), Kawasaki et al.
patent: 6420988 (2002-07-01), Azami et al.
patent: 6461899 (2002-10-01), Kitakado et al.
patent: 6469317 (2002-10-01), Yamazaki et al.
patent: 6492681 (2002-12-01), Koyama et al.
patent: 6498369 (2002-12-01), Yamazaki et al.
patent: 6506636 (2003-01-01), Yamazaki et al.
patent: 6563482 (2003-05-01), Yamazaki et al.
patent: 6580475 (2003-06-01), Yamazaki et al.
patent: 07-130652 (1995-05-01), None
patent: 2564725 (1996-12-01), None
Hatano et al., “A Novel Self-Aligned Gate-Overlapped LDD Poly-Si TFT WITH High Reliability and Performance”, IDEM Technical Digest 97, pp. 523-526.

Affiliated with

Also associated with

Rating

Semiconductor device and manufacturing method thereof does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor device and manufacturing method thereof, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and manufacturing method thereof will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3886040