Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2007-06-12
2007-06-12
Lebentritt, Michael (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C257SE21168
Reexamination Certificate
active
10788991
ABSTRACT:
A semiconductor device structure having a barrier layer comprising a conductive portion and a nonconductive portion is disclosed. The conductive portion includes a metal nitride compound and the nonconductive portion includes a metal oxide, metal oxynitride, metal carbide, or metal carbonitride compound. A method of forming the semiconductor device structure is also disclosed. The method comprises forming a barrier layer over a metallization layer and a dielectric layer in the semiconductor device structure. The barrier layer is formed by depositing a thin, metal layer over the metallization layer and the dielectric layer. The metal layer is exposed to a nitrogen atmosphere and the nitrogen reacts with portions of the metal layer over the metallization layer to form a conductive, metal nitride portion of the barrier layer. Portions of the metal layer over the dielectric layer react with carbon or oxygen in the dielectric layer to produce a nonconductive portion of the barrier layer.
REFERENCES:
patent: 2842438 (1958-07-01), Saarivirta et al.
patent: 5130274 (1992-07-01), Harper et al.
patent: 5904565 (1999-05-01), Nguyen et al.
patent: 6023102 (2000-02-01), Nguyen et al.
patent: 6077792 (2000-06-01), Farrar
patent: 6307266 (2001-10-01), Yung
patent: 6352917 (2002-03-01), Gupta et al.
patent: 6376370 (2002-04-01), Farrar
patent: 6420262 (2002-07-01), Farrar
patent: 6426289 (2002-07-01), Farrar
patent: 6841477 (2005-01-01), Uchibori
patent: 6849541 (2005-02-01), Hu et al.
patent: 6852624 (2005-02-01), Shingubara et al.
patent: WO 01/54192 (2001-07-01), None
Andricacos, Panos C., “Copper On-Chip Interconnections”, The Electrochemical Society Interface, Spring 1999, pp. 32 37, vol. 8, No. 1.
Braud et al., “Ultra Thin Diffusion Barriers for Cu Interconnections at the Gigabit Generation and Beyond”, VMIC Conference, Jun. 1996, pp. 174-179, 1996 ISMIC—106/96/0174(c).
de Felipe et al., “Electrical Stability and Microstructural Evolution in Thin Films of High Conductivity Copper Allows”, IEEE, 1999, IITC 99/293-295.
Ding et al., “Copper Barrier, Seed Layer and Planarization Technologies”, VMIC Conference, Jun. 1997, pp. 87-92, 1997 ISMIC—107/97/0087(c).
Godbey et al., “Copper Diffusion in Organic Polymer Resists and Inter-Level Dielectrics”, Thin Solid Films, Oct. 31, 1997 pp. 470-474, vols. 308-309.
Iijima et al. “Structure and Electrical Properites of Amorphous W-Si-N Barrier Layer for Cu Interconnections”, VMIC Conference, Jun. 1996, pp. 168-173, 1996 ISMIC—106/96/0168(c).
“International Conference on Metallurgical Coatings and Thin Films”, Program and Abstracts, Apr. 1997, pp. 309, 313.
“Improved Metallurgy for Wiring Very Large Scale Integrated Circuits”, International Technology Disclosures, Sep. 25, 1986, 1 page, vol. 4, No. 9.
Lyman et al., “Metallography, Structures and Phase Diagrams”, Metals Handbook, 8thEdition, date unknown, pp. 300-302, vol. 8, Metals Park, Ohio.
Marcadal et al., “OMCVD Copper Process for Dual Damascene Metallization”, VMIC Conference, Jun. 1997, pp. 93-98, 1997 ISMIC—107/97/0093(c).
Murarka et al., “Copper Interconnection Schemes: Elimination of the Need of Diffusion Barrier/Adhesion Promoter by the Use of Corrosion Resistant, Low Resistivity Doped Copper”, SPIE, Jan. 1994, pp. 80-90, vol. 2335.
Ryu et al., “Barriers for Copper Interconnections”, Solid State Technology, Apr. 1999, pp. 1-6, vol. 42, Issue 4, p. 53.
Saarivirta, Matti J., “High Conductivity Copper-Rich Cu-Zr Alloys”, Transactions of the Metallurgical Society of AIME, Jun. 1960, pp. 431-437, vol. 218, New York, NY.
Lebentritt Michael
Micro)n Technology, Inc.
Stevenson Andre′
TraskBritt
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