Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2007-06-05
2007-06-05
Iqbal, Nadeem (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
Reexamination Certificate
active
10801131
ABSTRACT:
A system-on-chip integrated circuit2is provided with multiple data processing circuits4, 6, 8each with an associated diagnostic interface circuit16, 18, 20connected via a diagnostic transaction bus14to a diagnostic transaction master circuit12. The diagnostic master transaction circuit12issues diagnostic transaction requests to the diagnostic interface circuits16, 18, 20. If the associated data processing circuits4, 6, 8are powered-down, or otherwise non responsive, then the diagnostic interface circuit16, 18, 20returns a diagnostic bus transaction error signal to the diagnostic transaction master circuit12. A sticky-bit latch30within each diagnostic interface circuit16, 18, 20serves to record a power-down event and force generation of the diagnostic bus transaction error signal until that sticky bit is cleared by the diagnostic mechanisms. This ensure the diagnostic mechanisms are made aware of the power-down event so they may take any appropriate remedial action that might be necessary as a result of that power-down event.
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Allue Conrado Blasco
Grisenthwaite Richard Roy
Kimelman Paul
Swaine Andrew Brookfield
ARM Limited
Iqbal Nadeem
Nixon & Vanderhye P.C.
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