Semiconductor device with power down arrangement for reduce...

Static information storage and retrieval – Powering

Reexamination Certificate

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C365S063000, C365S229000, C365S230030, C365S233100

Reexamination Certificate

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11483649

ABSTRACT:
A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.

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patent: 5804893 (1998-09-01), Fujioka
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patent: 9-161481 (1997-06-01), None
patent: 11-003586 (1999-01-01), None

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