Nonvolatile semiconductor memory and manufacturing method...

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257S391000, C257S392000, C257S524000

Reexamination Certificate

active

10868773

ABSTRACT:
A semiconductor memory has a memory cell matrix encompassing (a) device isolation films running along the column-direction, arranged alternately between the memory cell transistors aligned along the row-direction, (b) first conductive layers arranged along the row and column-directions, top surfaces of the first conductive layers lie at a lower level than top surfaces of the device isolation films, (c) an inter-electrode dielectric arranged both on the device isolation films and the first conductive layers so that the inter-electrode dielectric can be shared by the memory cell transistors belonging to different cell columns' relative dielectric constant of the inter-electrode dielectric is higher than relative dielectric constant of the device isolation films, and (d) a second conductive layer running along the row-direction, arranged on the inter-electrode dielectric. Here, upper corners of the device isolation films are chamfered.

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patent: 2001-168306 (2001-06-01), None
J.-D. Lee, et al., IEEE Electron Device Letters, vol. 23, No. 5, pp. 264-266, “Effects of Floating-Gate Interference on NAND Flash Memory Cell Operation”, May 2002.
W.-H. Lee, et al., Symposium on VLSI Technology Digest of Technical Papers, pp. 117-118, “A Novel High K Inter-Poly Dielectric(IPD), AI2O3for Low Voltage/High Speed Flash Memories: Erasing in MSECS at 3.3V”, 1997.

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