Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
2007-02-13
2007-02-13
Dildine, R. Stephen (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C714S769000
Reexamination Certificate
active
10714931
ABSTRACT:
Data is read from a recording medium and the reproduced data is deinterleaved and stored to a first memory while input/output to/from the first memory is arbitrated. It is determined whether a predetermined number of data units is stored to the first memory. Based on the result data, it is determined whether transfer of the data stored in first memory to a second memory is permitted. If data transfer is permitted, the reproduced data is transferred from the first memory to the second memory, during which time input/output to/from the second memory is arbitrated. The reproduced data stored to the second memory is then error corrected, and user data contained in the error corrected reproduction data is externally output from the second memory.
REFERENCES:
patent: 2004/0257900 (2004-12-01), Takagi et al.
patent: 0 992 994 (1998-12-01), None
patent: 09139026 (1997-05-01), None
patent: 11110920 (1999-04-01), None
patent: 2002-521789 (2002-07-01), None
patent: 99/31661 (1999-06-01), None
patent: 00/07300 (2000-02-01), None
Hashimoto Yuichi
Kimura Naohiro
Takagi Yuji
Usui Makoto
Yamamoto Yoshikazu
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