Dual-target block register allocation

Details Dual-target block register allocation Dual-target block register allocation

2007-12-11

2007-12-11

Kindred, Alford (Department: 2181)

Electrical computers and digital processing systems: processing

Dynamic instruction dependency checking, monitoring or...

Scoreboarding, reservation station, or aliasing

C712S216000, C712S214000, C712S215000

Reexamination Certificate

active

09968278

ABSTRACT:
A method and apparatus for dual-target register allocation is described, intended to enable the efficient mapping/renaming of registers associated with instructions within a pipelined microprocessor architecture.

REFERENCES:
patent: 5497499 (1996-03-01), Garg et al.
patent: 5671383 (1997-09-01), Valentine
patent: 5694564 (1997-12-01), Alsup et al.
patent: 6324640 (2001-11-01), Le et al.

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