Multifunction hexadecimal instructions

Details Multifunction hexadecimal instructions Multifunction hexadecimal instructions

2007-08-07

2007-08-07

Chan, Eddie (Department: 2183)

Electrical computers and digital processing systems: processing

Processing control

Arithmetic operation instruction processing

C708S501000

Reexamination Certificate

active

10435982

ABSTRACT:
A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the fused functions. Both binary and hexadecimal floating-point instructions are supported for a total of 6 formats. The floating-point unit is capable of performing a multiply-add instruction for hexadecimal or binary every cycle with a latency of 5 cycles. This supports two architectures with two internal formats with their own biases. This has eliminated format conversion cycles and has optimized the width of the dataflow. The unit is optimized for both hexadecimal and binary floating-point architecture supporting a multiply-add/subtract per cycle.

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Siegel et al. “IBM's S/390 G5 microprocessor design.” 1999 IEEE. pp. 12-23.

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