Multi-level memory cell array with lateral floating spacers

Details Multi-level memory cell array with lateral floating spacers Multi-level memory cell array with lateral floating spacers

2007-02-20

2007-02-20

Parker, Kenneth (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S316000, C257S317000, C257SE27084, C257SE27094, C257SE27098, C365S185100, C365S185030, C365S185050, C365S185330

Reexamination Certificate

active

10985673

ABSTRACT:
An array of multi-level non-volatile memory transistors features a transistor construction with a conductive polysilicon control gate having opposed sidewalls insulatively spaced just above the substrate. Conductive polysilicon spacers are separated from the opposed sidewalls by thin tunnel oxide. Source and drain implants are beneath or slightly outboard of the spacers. Insulative material is placed over the structure with a hole cut above the control gate for contact by a gate electrode connected to, or part of, a conductive word line. The array has auxiliary low voltage transistors which may be made at the same time as the formation of the memory transistors. The auxiliary transistors apply opposite phase clock pulses to source and drain electrodes of transistors in the array so that first one side of each memory transistor may be written to, or read, then the other side.

REFERENCES:
patent: 6178113 (2001-01-01), Gonzalez et al.
patent: 6323088 (2001-11-01), Gonzalez et al.
patent: 6501680 (2002-12-01), Kwon
patent: 6531360 (2003-03-01), Lee
patent: 2002/0153555 (2002-10-01), Manabe et al.

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