Method for forming raised structures by controlled selective...

Semiconductor device manufacturing: process – Formation of semiconductive active region on any substrate

Reexamination Certificate

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

C257SE21001

Reexamination Certificate

active

09816962

ABSTRACT:
Raised structures comprising overlying silicon layers formed by controlled selective epitaxial growth, and methods for forming such raised-structure on a semiconductor substrate are provided. The structures are formed by selectively growing an initial epitaxial layer of monocrystalline silicon on the surface of a semiconductive substrate, and forming a thin film of insulative material over the epitaxial layer. A portion of the insulative layer is removed to expose the top surface of the epitaxial layer, with the insulative material remaining along the sidewalls as spacers to prevent lateral growth. A second epitaxial layer is selectively grown on the exposed surface of the initial epitaxially grown crystal layer, and a thin insulative film is deposited over the second epitaxial layer. Additional epitaxial layers are added as desired to provide a vertical structure of a desired height comprising multiple layers of single silicon crystals, each epitaxial layer have insulated sidewalls, with the uppermost epitaxial layer also with an insulated top surface. The resultant structure can function, for example, as a vertical gate of a DRAM cell, elevated source/drain structures, or other semiconductor device feature.

REFERENCES:
patent: 4442178 (1984-04-01), Kimura et al.
patent: 4554570 (1985-11-01), Jastrzebski et al.
patent: 4757027 (1988-07-01), Vora
patent: 4948745 (1990-08-01), Pfiester et al.
patent: 4963506 (1990-10-01), Liaw et al.
patent: 5057888 (1991-10-01), Fazan et al.
patent: 5079180 (1992-01-01), Rodder et al.
patent: 5087586 (1992-02-01), Chan et al.
patent: 5122476 (1992-06-01), Fazan et al.
patent: 5156987 (1992-10-01), Sandhu et al.
patent: 5198378 (1993-03-01), Rodder et al.
patent: 5200352 (1993-04-01), Pfiester
patent: 5208172 (1993-05-01), Fitch
patent: 5241193 (1993-08-01), Pfiester et al.
patent: 5304834 (1994-04-01), Lynch
patent: 5308782 (1994-05-01), Mazure et al.
patent: 5312768 (1994-05-01), Gonzalez
patent: 5316962 (1994-05-01), Matsuo et al.
patent: 5360760 (1994-11-01), Hayashi
patent: 5376562 (1994-12-01), Fitch et al.
patent: 5393681 (1995-02-01), Witek et al.
patent: 5397909 (1995-03-01), Moslehi
patent: 5460994 (1995-10-01), Kim
patent: 5483094 (1996-01-01), Sharma et al.
patent: 5497017 (1996-03-01), Gonzales
patent: 5547889 (1996-08-01), Kim
patent: 5574299 (1996-11-01), Kim
patent: 5578850 (1996-11-01), Fitch et al.
patent: 5595920 (1997-01-01), Miyawaki et al.
patent: 5600161 (1997-02-01), Gonzalez et al.
patent: 5612230 (1997-03-01), Yuzurihara et al.
patent: 5612563 (1997-03-01), Fitch et al.
patent: 5627395 (1997-05-01), Witek et al.
patent: 5641694 (1997-06-01), Kenney
patent: 5677573 (1997-10-01), Prall et al.
patent: 5691212 (1997-11-01), Tsai et al.
patent: 5753555 (1998-05-01), Hada
patent: 5753947 (1998-05-01), Gonzalez
patent: 5780327 (1998-07-01), Chu et al.
patent: 5780906 (1998-07-01), Wu et al.
patent: 5831334 (1998-11-01), Prall et al.
patent: 5841150 (1998-11-01), Gonzalez et al.
patent: 5843826 (1998-12-01), Hong
patent: 5849077 (1998-12-01), Kenney
patent: 5863826 (1999-01-01), Wu et al.
patent: 5864180 (1999-01-01), Hori et al.
patent: 5872374 (1999-02-01), Tang et al.
patent: 5886382 (1999-03-01), Witek
patent: 5888294 (1999-03-01), Min et al.
patent: 5902125 (1999-05-01), Wu
patent: 5933738 (1999-08-01), Kao et al.
patent: 5945698 (1999-08-01), Prall
patent: 5949105 (1999-09-01), Moslehi
patent: 5953605 (1999-09-01), Kodama
patent: 5963822 (1999-10-01), Saihara et al.
patent: 5970351 (1999-10-01), Takeuchi
patent: 5994735 (1999-11-01), Maeda et al.
patent: 5998248 (1999-12-01), Ma et al.
patent: 5998844 (1999-12-01), Prall et al.
patent: 6001697 (1999-12-01), Chang et al.
patent: 6018176 (2000-01-01), Lim
patent: 6037202 (2000-03-01), Witek
patent: 6051473 (2000-04-01), Ishida et al.
patent: 6057200 (2000-05-01), Prall et al.
patent: 6072226 (2000-06-01), Thakur et al.
patent: 6074478 (2000-06-01), Oguro
patent: 6090691 (2000-07-01), Ang et al.
patent: 6096596 (2000-08-01), Gonzalez
patent: 6127232 (2000-10-01), Chatterjee et al.
patent: 6143608 (2000-11-01), He et al.
patent: 6159852 (2000-12-01), Nuttall et al.
patent: 6228733 (2001-05-01), Lee et al.
patent: 6232641 (2001-05-01), Miyano et al.
patent: 6248637 (2001-06-01), Yu
patent: 6268621 (2001-07-01), Emmi et al.
patent: 6300251 (2001-10-01), Pradeep et al.
patent: 6319782 (2001-11-01), Nakabayashi
patent: 6391692 (2002-05-01), Nakamura
patent: 6392271 (2002-05-01), Alavi et al.
patent: 6433382 (2002-08-01), Orlowski et al.
patent: 6448129 (2002-09-01), Cho et al.
patent: 6455377 (2002-09-01), Zheng et al.
patent: 6458699 (2002-10-01), Nuttall et al.
patent: 6479875 (2002-11-01), Gonzalez
patent: 6492232 (2002-12-01), Tang
patent: 6495437 (2002-12-01), Yu
patent: 6506649 (2003-01-01), Fung et al.
patent: 6509239 (2003-01-01), Nuttall et al.
patent: 6594293 (2003-07-01), Bulsara
patent: 6620710 (2003-09-01), Kamins
patent: 6660650 (2003-12-01), Konecni
patent: 2001/0040292 (2001-11-01), Hahn et al.
patent: 2002/0072181 (2002-06-01), Tseng
patent: 2002/0093054 (2002-07-01), Yeh et al.
patent: 2004/0175893 (2004-09-01), Vatus
patent: 401286361 (1989-11-01), None
patent: 02001068671 (2001-03-01), None
Blanton, T.N., et al., The Rigaku Journal, vol. 13, No. 1, 1996, pp. 3-7.
Van Zant, Peter, Microchip Fabrication, A Practical Guide to Semiconductor Processing, 4thEd., McGraw-Hill, New York, NY (2000), Chapter 12 at pp. 380-388.
Wolf et al., Silicon Processing for the VLSI Era, vol. 1: Process Technology, 2ndEd., Lattice Press, Sunset Beach, CA (2000), Chapter 7 (Silicon Epitaxial Grwoth and Silicon on Insulator) at pp. 225-264.
Ginsberg et al., “Selective epitaxial growth of silicon and some potential application,”IBM J. Res Develop. 34(6): Nov. 1990.
Wolf, et al., Silicon Processing for the VLSI Era, vol. 1: Processing Technology, 1986, p. 155-156.

LandOfFree

Say what you really think

Search LandOfFree.com for the USA inventors and patents. Rate them and share your experience with other people.

Rating

Method for forming raised structures by controlled selective... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method for forming raised structures by controlled selective..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method for forming raised structures by controlled selective... will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFUS-PAI-O-3876899

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.