Pseudo multiport data memory has stall facility

Details Pseudo multiport data memory has stall facility Pseudo multiport data memory has stall facility

2007-12-11

2007-12-11

Peugh, Brian R. (Department: 2187)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C710S242000

Reexamination Certificate

active

10515453

ABSTRACT:
A computer memory arrangement comprises a first plurality of input port facilities that are collectively coupled through a first router facility to selectively feed a first plurality of memory modules. It furthermore includes an output port facility that is fed collectively by the first plurality of memory modules. further ,the computer memory arrangement includes an access detection facility for detecting simultaneous and conflicting accesses occurring through more than one of the first plurality of input port facilities for a particular memory,module, and for thereupon allowing only a single one among the simultaneous and conflicting accesses while generating a stall signal for signaling a mandatory stall signal to any request source pertaining to another request.

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