Register file with integrated routing to execution units for...

Details Register file with integrated routing to execution units for... Register file with integrated routing to execution units for...

2007-12-18

2007-12-18

Bataille, Pierre-Michel (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Control technique

C718S108000, C711S156000

Reexamination Certificate

active

10388384

ABSTRACT:
A multi-context register file for use in a multi-threaded processor includes at least one multi-context register file cell having internal routing functionality.

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patent: 6694347 (2004-02-01), Joy et al.
Tremblay et al., “A Three Dimensional Register File for Superscalar Processors”, Proceedings of the 28th Annual Hawaii International Conference on Systems Sciences, Jan. 1995, pp. 191-201.
Kavi et al.: “A Decoupled Scheduled Dataflow Multithreaded Architecture”, IEEE 1999 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '99) Jun. 23-25, 1999.

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