Method and metric for low power standard cell logic synthesis

Details Method and metric for low power standard cell logic synthesis Method and metric for low power standard cell logic synthesis

2007-08-21

2007-08-21

Chiang, Jack (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

11009488

ABSTRACT:
Pseudo area values, which represent standard cell power dissipation, are substituted for physical standard cell areas in a standard cell library. As a result, when a logic synthesizer synthesizes a gate level netlist from hardware description language (HDL) code, the synthesized netlist will describe a logic block that has minimal power dissipation.

REFERENCES:
patent: 6567971 (2003-05-01), Banzhaf et al.
patent: 6609244 (2003-08-01), Kato et al.
patent: 2002/0069396 (2002-06-01), Bhattacharya et al.
patent: 2004/0186703 (2004-09-01), Radjassamy
patent: 2004/0210857 (2004-10-01), Srinivasan

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