Semiconductor memory device with redundancy circuit

Details Semiconductor memory device with redundancy circuit Semiconductor memory device with redundancy circuit

2007-08-07

2007-08-07

Zarabian, Amir (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S189080, C365S191000, C365S201000, C365S115000

Reexamination Certificate

active

11001026

ABSTRACT:
A semiconductor device has a memory cell, decoders, a redundancy circuit and a mode setting circuit. The memory cell array has word lines including a redundant word line, bit lines and memory cells. A row decoder selects the word lines in response to a row address. Further, the row address decoder selects the redundant word line when a replacement signal is received. A column decoder selects the bit lines in response to a column address. A row address redundancy circuit stores a redundant row address. The row address redundancy circuit provides the replacement signal when the redundant row address corresponds to the received address. The mode setting circuit receives a mode signal having a normal mode and a test mode. The mode setting circuit outputs the replacement signal to the row decoder when the mode signal is in the normal mode, and prohibits an output of the replacement signal.

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patent: 07-220495 (1995-08-01), None

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