Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2007-11-20
2007-11-20
Ha, Nathan W. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
Reexamination Certificate
active
11171399
ABSTRACT:
A memory device includes multiple fins formed adjacent to one another, a source region, a drain region, a gate, a wordline, and a bitline contact. At least one of the multiple fins is doped with a first type of impurities and at least one other one of the fins is doped with a second type of impurities. The source region is formed at one end of each of the fins and the drain region is formed at an opposite end of each of the fins. The gate is formed over two of the multiple fins, the wordline is formed over each of the multiple fins, and a bitline contact is formed adjacent at least one of the multiple fins.
REFERENCES:
patent: 4996574 (1991-02-01), Shirasaki
patent: 6765303 (2004-07-01), Krivokapic et al.
patent: 6787406 (2004-09-01), Hill et al.
patent: 6855588 (2005-02-01), Liao et al.
patent: 6872647 (2005-03-01), Yu et al.
patent: 2003/0102518 (2003-06-01), Fried et al.
patent: 2004/0108545 (2004-06-01), Ando
patent: 2004/0119100 (2004-06-01), Nowak et al.
patent: 2004/0188705 (2004-09-01), Yeo et al.
patent: 2004/0227187 (2004-11-01), Cheng et al.
patent: 2005/0001273 (2005-01-01), Bryant et al.
patent: 2005/0077574 (2005-04-01), Mouli
patent: 2005/0128787 (2005-06-01), Mouli
patent: 2005/0186738 (2005-08-01), Hofmann et al.
patent: 2004-281845 (2004-10-01), None
Co-pending U.S. Appl. No. 10/887,083, filed Jul. 9, 2004, entitled “Systems and Methods for forming dense n-channel and p-channel fins using shadow implanting”, 34 pages of specification.
Digh Hisamoto et al., “FinFET—A self-Aligned Double-Gage MOSFET Scalable to 20 nm,” IEEE Transactions on Electron Devices, vol. 47, No. 12, Dec. 2000, pp. 2320-2325.
Yank-Kyu Choi et al., “Sub-20nm CMOS FinFET Technologies,” 2001 IEEE, IEDM, pp. 421-424.
Xuejue Huang et al., “Sub-50 nm P-Channel FinFET,” IEEE Transactions on Electron Devices, vol. 48, No. 5, May 2001, pp. 880-886.
Xuejue Huang et al., “Sub 50-nm FinFET: PMOS,” 1999 IEEE, IEDM, pp. 67-70.
Yang-Kyu Choi et al., “Nanoscale CMOS Spacer FinFET for the Terabit Era,” IEEE Electron Device Letters, vol. 23, No. 1, Jan. 2002, pp. 25-27.
J. I. Bergman et al.: “RTD/CMOS Nanoelectric Circuits: Thin-Film InP-Based Resonant Tunneling Diodes Integrated with CMOS Circuits,” IEEE Electron Device Letters, vol. 20, No. 3, Mar. 1999, pp. 119-122.
A. Seabaugh et al.: “Transistors and Tunnel Diodes For Analog/Mixed-Signal Circuits and Embedded Memory,” IEDM, Dec. 8, 1998, 4 pages.
Hill Wiley Eugene
Yu Bin
Advanced Micro Devices , Inc.
Ha Nathan W.
Harrity & Snyder LLP
LandOfFree
SRAM formation using shadow implantation does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with SRAM formation using shadow implantation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and SRAM formation using shadow implantation will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3869787