Semiconductor damascene trench and methods thereof

Details Semiconductor damascene trench and methods thereof Semiconductor damascene trench and methods thereof

2007-02-20

2007-02-20

Lindsay, Jr., Walter (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S275000, C438S197000, C438S586000, C257S211000, C257S390000

Reexamination Certificate

active

10883522

ABSTRACT:
A memory device cell layout, a computer system comprising a memory device having a particular cell layout, and methods of fabricating static memory cells and semiconductor devices embodying the cells are also provided. In accordance with one embodiment of the present invention, a memory device cell layout is provided comprising four active areas positioned between selected ones of the gates and local interconnects associated with different damascene trenches of the device.

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