Transistor fabrication using double etch/refill process

Details Transistor fabrication using double etch/refill process Transistor fabrication using double etch/refill process

2007-06-05

2007-06-05

Smith, Matthew (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S150000, C438S162000, C438S163000, C438S164000, C257SE29260

Reexamination Certificate

active

11101354

ABSTRACT:
A semiconductor fabrication process includes forming a gate electrode (120) overlying a gate dielectric (110) overlying a semiconductor substrate (102). First spacers (124) are formed on sidewalls of the gate electrode (120). First s/d trenches (130) are formed in the substrate (102) using the gate electrode (120) and first spacers (124) as a mask. The first s/d trenches (130) are filled with a first s/d structure (132). Second spacers (140) are formed on the gate electrode (120) sidewalls adjacent the first spacers (124). Second s/d trenches (150) are formed in the substrate (102) using the gate electrode (120) and the second spacers (140) as a mask. The second s/d trenches (150) are filled with a second s/d structure (152). Filling the first and second s/d trenches (130, 150) preferably includes growing the s/d structures using an epitaxial process. The s/d structures (132, 152) may be stress inducing structures such as silicon germanium for PMOS transistors and silicon carbon for NMOS transistors.

REFERENCES:
patent: 5908313 (1999-06-01), Chau et al.
patent: 6342421 (2002-01-01), Mitani et al.
patent: 6599789 (2003-07-01), Abbott et al.
patent: 6605498 (2003-08-01), Murthy et al.
patent: 6621131 (2003-09-01), Murthy et al.

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