Semiconductor memory device including MOS transistors each...

Details Semiconductor memory device including MOS transistors each... Semiconductor memory device including MOS transistors each...

2007-12-25

2007-12-25

Purvis, Sue A. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S391000, C257S315000, C257SE21689, C257SE21691, C257S316000, C365S185050, C365S185130

Reexamination Certificate

active

10753324

ABSTRACT:
A semiconductor memory device includes a plurality of memory cells, a plurality of local bit lines, a global bit line, a first switch element, and a holding circuit. The memory cell includes first and second MOS transistors. The first MOS transistor has a charge accumulation layer and a control gate. The second MOS transistor has one end of its current path connected to one end of a current path of the first MOS transistor. The local bit line connects other end of the current paths of the first MOS transistors. The first switch element makes a connection between the local bit lines and the global bit line. The holding circuit is connected to the global bit line and holds data to be written into the memory cells.

REFERENCES:
patent: 5818761 (1998-10-01), Onakado et al.
patent: 6222774 (2001-04-01), Tanzawa et al.
patent: 6256227 (2001-07-01), Atsumi et al.
patent: 1999-0048773 (1999-07-01), None
Wei-Hua Liu et al., A 2-Transistor Source-select (2TS) Flash EEPROM for 1.8V-Only Applications, Non-volatile Semiconductor Memory Workshop 4.1, 1997.
U.S. Appl. No. 10/753,324, filed Jan. 9, 2004, Umezawa et al.
U.S. Appl. No. 11/733,796, filed Apr. 11, 2007, Kanda et al.

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