Method and apparatus for detecting timing exception path and...

Details Method and apparatus for detecting timing exception path and... Method and apparatus for detecting timing exception path and...

2007-11-20

2007-11-20

Kik, Phallaka (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C703S016000, C703S019000, C714S033000, C714S051000, C714S055000, C714S724000, C714S741000, C324S528000, C324S532000, C324S537000, C702S059000, C702S118000, C702S125000

Reexamination Certificate

active

11063773

ABSTRACT:
A selector selects an FF pair (FFs, FFe) in circuit information, a calculator calculates value-capturing condition data at FFe, a divider divides a path set that matches the value-capturing condition data from a set of paths between the FF pair (FFs, FFe), and a multi-cycle path detector determines whether all the paths in the path set are multi-cycle paths. When the path set is a multi-cycle path, it is added to a timing exception path list that is output by an output unit.

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Marinescu et al., “High-Level Automatic Pipelining for Sequential Circuits”, Proceedings of 14th International Symposium on Systems Synthesis, 2001, pp. 215-220.

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