Memory circuit with shared redundancy

Details Memory circuit with shared redundancy Memory circuit with shared redundancy

2007-02-20

2007-02-20

Le, Thong Q. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Bad bit

C365S230030, C365S189050

Reexamination Certificate

active

10745294

ABSTRACT:
An integrated circuit memory including at least two banks each provided with an array of storage elements having at least one redundancy column and each associated with specific sense amplifiers, a row of input/output buffer circuits common to the memory banks, and for each memory bank, a circuit for assigning the redundancy column to an input/output line connected to one of said buffers. The assigning can be performed, for a line of current rank, towards the columns of preceding rank and towards the columns of following rank.

REFERENCES:
patent: 5323348 (1994-06-01), Kinoshita et al.
patent: 5506807 (1996-04-01), Ferrant et al.
patent: 5999450 (1999-12-01), Dallabora et al.
patent: 6151263 (2000-11-01), Kyung et al.
patent: 6304501 (2001-10-01), Ooishi
French Search Report from French Patent Application No. 00 16035, filed Dec. 8, 2000.

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