Semiconductor memory device and electronic equipment

Static information storage and retrieval – Read/write circuit

Reexamination Certificate

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Details

C365S185240, C365S189070, C365S236000, C365S204000

Reexamination Certificate

active

11401369

ABSTRACT:
A semiconductor memory device has a memory cell array in which a plurality of nonvolatile memory cells are arranged. The memory device also has word lines, bit lines connected with the memory cells by a virtual grounding scheme, a row decoder, shift registers, a write voltage control circuit for controlling voltages to be applied to bit lines, and a write voltage applying circuit for applying voltages to the bit lines. The write voltage control circuit controls the write voltage applying circuit such that when writing data1to a memory cell, different voltages V0and VP are applied to two bit lines associated with the memory cell, while a same voltage V0or VP is applied to the two bit lines when writing data0to the memory cell.

REFERENCES:
patent: 6687155 (2004-02-01), Nagasue
patent: 6912160 (2005-06-01), Yamada
patent: 2002-279789 (2002-09-01), None
patent: 2004-273093 (2004-09-01), None

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