Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2007-11-27
2007-11-27
Baderman, Scott (Department: 2114)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S006130
Reexamination Certificate
active
10692193
ABSTRACT:
The invention provides replacement operation code for specific defective lines of operation code contained in a ROM often on an ASIC chip which code is used in a processor. ROM memory constitutes the best use of chip space and is the most economical to manufacture of all of the various options. ROM memory is not changeable after it is set in ROM and, hence, if there is any change in the code (hereinafter sometimes faulty code) required after the code has been incorporated in the ROM memory, such change cannot be made in the ROM itself without replacing the entire ROM. The present invention allows change in any specific lines of faulty contained in ROM without replacing the entire ROM, and provides for changing only the faulty lines of code. It also allows the new code to have the same, more, or fewer lines than the faulty code.
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“Instruction Intercept for a Read-Only Storage Controlled Processor” T.D. Herman and G.J. Watkins, IBM Technical Disclosure Bulletin. vol. 16, No. 8, Jan. 1974, pp. 2506-2507.
Baderman Scott
Driggs, Hogg & Fry Co. LPA
Hogg William N.
International Business Machines - Corporation
Lohn Joshua
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