SRAM device having high aspect ratio cell boundary

Details SRAM device having high aspect ratio cell boundary SRAM device having high aspect ratio cell boundary

2007-06-19

2007-06-19

Purvis, Sue A. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Gate arrays

C257S204000, C257S903000

Reexamination Certificate

active

10818133

ABSTRACT:
A static random access memory (SRAM) device including a substrate and an SRAM unit cell. The substrate includes an n-doped region interposing first and second p-doped regions. The SRAM unit cell includes: (1) a first pass-gate transistor and a first pull-down transistor located at least partially over the first p-doped region; (2) first and second pull-up transistors located at least partially over the n-doped region; and (3) a second pass-gate transistor, a second pull-down transistor, and first and second read port transistors, all located at least partially over the second p-doped region. A boundary of the SRAM unit cell comprises first and second primary dimensions having an aspect ratio of at least about 3.2.

REFERENCES:
patent: 6822300 (2004-11-01), Nii
patent: 2001/0043487 (2001-11-01), Nii et al.
patent: 2004/0120209 (2004-06-01), Lee et al.

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