Memory system and test method therefor

Details Memory system and test method therefor Memory system and test method therefor

2007-10-09

2007-10-09

Britt, Cynthia (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C365S201000

Reexamination Certificate

active

11173735

ABSTRACT:
A memory system (1A) includes a memory section (2A) and a memory control section (3A). The memory section (2A) includes a test circuit (4A), a data register (5A), a data output section (6A), and a memory core section (9A). Data DI is held in the data resistor (5A). The test circuit (4A) outputs write inhibit signal WINH to the memory core section (9A) in response to test signal TEST. Write instruction recognition signal WR which recognizes that a write command is inputted into the memory section (2A) and select signal S are inverted and, in response thereto, retained data DR of the data register (5A) is outputted as output data DO from the data output section (6A). Thus, it is possible to test whether generation, propagation, or recognition operation of a write command CMD and the data DI is normal or not without executing the operation of writing data into a memory cell of the memory section.

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