Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-08-28
2007-08-28
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
Reexamination Certificate
active
10911317
ABSTRACT:
Methods and apparatuses for automated synthesis transformation for carry save optimization and/or for the correction of dropped truncation after widening an adder. In one embodiment of the present invention, a correction input is automatically generated for a widened adder to correct the dropping or truncation of result bits that is performed by the adder before the widening. In one example the dropped result bits are part of the user's HDL specification. In another example the carry save optimization is enabled by a retiming operation. In one embodiment of the present invention, one or more logic operators between adders are pushed (e.g., forward or backward) across at least one of the adders so that the adders can be collapsed for carry save optimization. In one embodiment, an adder followed by a comparator is transformed to use a carry save adder followed by a comparator so that the carry chain in the original adder can be eliminated.
REFERENCES:
patent: 6772399 (2004-08-01), Saluja et al.
patent: 6785872 (2004-08-01), Carter
Kim et al., “Circuit Optimization Using Carry-Save-Adder Cells”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, No. 10, Oct. 1998.
Signal Representation Guided Synthesis Using Carry-Save Adders For Synchronous Data-path Circuits, by Zhan Yu, et al.
Arithmetic Optimization Using Carry-Save-Adders, by Taewhan Kim, et al.
Quantum Carry-Save Arithmetic, by Phil Gossett, Aug. 29, 1998.
McElvain Kenneth S.
Rickel David
Bowers Brandon
Chiang Jack
Synplicity, Inc.
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