Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-12-25
2007-12-25
Whitmore, Stacy A (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
11169362
ABSTRACT:
A system that routes nets within an integrated circuit. During operation, the system receives a representation for the integrated circuit, which includes block boundaries for physical partitions of the IC generated from a hierarchical design placement of the integrated circuit. The system then classifies each net in the integrated circuit based on the location of pins associated with the net. Next, the system generates routing constraints for each net based on the classification of the net and applies a feedthrough constraint to the physical partitions to restrict nets from feeding through physical partition boundaries. Finally, the system routes each net using the routing constraints for the net and the feedthrough constraints for the physical partitions. This routing is performed based on these block boundaries prior to finalizing the hierarchical design placement, thereby facilitating early detection of congestion or timing violations which can be corrected early in the design process.
REFERENCES:
patent: 5784289 (1998-07-01), Wang
patent: 2002/0087940 (2002-07-01), Greidinger et al.
patent: 2003/0009734 (2003-01-01), Burks et al.
Kaul Neeraj
Rashingkar Balkrishna
Tseng Anthony Y.
Tseng Wei-Chih
Dimyan Magid Y.
Park, Vaughn & Fleming LLP
Synopsys Inc.
Whitmore Stacy A
Wong Gilbert
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