Method and system to encode and decode wide data words

Details Method and system to encode and decode wide data words Method and system to encode and decode wide data words

2007-06-12

2007-06-12

Baker, Stephen M. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S801000, C714S805000

Reexamination Certificate

active

10742595

ABSTRACT:
A parity generation circuit includes a plurality of bit-generation circuits. Each bit-generation circuit receives respective data bits and a respective hard latch signal, and operates to generate a parity signal indicating the parity of the corresponding data bits when the hard latch signal is inactive. Each bit-generation circuit drives the parity signal to a set value when the hard latch signal is active. An output circuit is coupled to the bit-generation circuits to receive the parity signals and operates to generate an output parity signal in response to the parity signals from the bit-generation circuits.

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