Etching method in a semiconductor processing and etching...

Details Etching method in a semiconductor processing and etching... Etching method in a semiconductor processing and etching...

2007-12-18

2007-12-18

Deo, Duy-Vu N (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S707000, C438S714000, C438S719000, C438S720000, C438S721000

Reexamination Certificate

active

11518080

ABSTRACT:
Disclosed is an etching method for semiconductor processing by which a pattern loading phenomenon is reduced. First, plasma is generated while setting a bias power applied to a wafer to zero and applying a source power. After a predetermined time period, an etching process is implemented onto a predetermined layer formed on the wafer by setting the bias power to a predetermined value. Since by-products generated during preceding etching processes can be readily removed during an etching using plasma, an etching process change due to a difference of pattern densities can be reduced. In addition, a progressive pattern loading generated as the number of processed wafers increase, can be prevented.

REFERENCES:
patent: 6156629 (2000-12-01), Tao et al.
patent: 6432834 (2002-08-01), Kim
patent: 6566270 (2003-05-01), Liu et al.

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