Series fed amplified antenna reflect array

Details Series fed amplified antenna reflect array Series fed amplified antenna reflect array

2007-11-20

2007-11-20

Nguyen, Hoang V. (Department: 2821)

Communications: radio wave antennas

Antennas

Balanced doublet - centerfed

C343S816000

Reexamination Certificate

active

11508085

ABSTRACT:
A reflect array antenna. The array includes a plurality of unit cells. Each cell includes a first dipole antenna having a first orientation and a first polarization; a second dipole antenna having a second orientation and a second polarization; and an amplifier input coupled inline to said first dipole antenna and output coupled inline to said second dipole antenna. The array further includes N first dipole antennas having a first orientation and a first polarization; M second dipole antennas having a second orientation and a second polarization; and a plurality of unit cells, each cell including an amplifier input coupled inline to a first dipole antenna and output coupled inline to a second dipole antenna. The second orientation and the second polarization are orthogonal to the first orientation and the first polarization. Each amplifier includes a transistor with an input terminal and first and second output terminals. Each input terminal is connected to the first dipole antenna and the output terminals are coupled to the second dipole antenna. The first and second terminals are adapted to be coupled to second and first terminals respectively of a neighboring cell in the array. A direct current bias for the array is applied via the second dipole antenna. Input bias for the transistors is applied via the first dipole antenna. A unique gate bias voltage for each transistor in the array is provided on a row-by-row basis via a voltage divider network. The voltage divider network includes (N−1) first resistors Rbconnected in series to a first source of supply potential, where N is the number of rows in the array. Each of the resistors is connected to provide an input voltage to one of the transistors in the array. The resistive network further includes M second resistors RLconnected to a respective one of the second dipoles antennas, where M is the number of columns in the array. The array is fabricated by via a metallization pattern which is disposed on a first substrate to provide a chip. The chip is secured to a second substrate with a bonding agent. In the best mode, the bonding agent is an anisotropic electrically conductive bonding film that allows current to flow along a path orthogonal to a surface of the array while blocking current flow parallel to the surface of the array.

REFERENCES:
patent: 6005530 (1999-12-01), Jovanovich et al.
patent: 6396449 (2002-05-01), Osterhues et al.
patent: 6870513 (2005-03-01), Deng et al.

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