Compact decode and multiplexing circuitry for a multi-port...

Details Compact decode and multiplexing circuitry for a multi-port... Compact decode and multiplexing circuitry for a multi-port...

2007-02-06

2007-02-06

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Addressing

Multiple port access

C365S230060, C365S189050, C365S230030

Reexamination Certificate

active

11200942

ABSTRACT:
A memory array for a multi-port memory having a common memory interface and a plurality of memory ports through which the memory array is accessed is provided. The memory array includes (r·s·t) memory locations with the memory array organized as a first memory sub-array accessible through a first of the plurality of memory ports as a (m×t) memory array and organized as a second memory sub-array accessible through a second of the plurality of memory ports as a (n×t) memory array. Both m and n are multiples of a value r, and the sum of (m/r) and (n/r) is equal to s. The memory array further organized as a common memory array accessible through the common memory interface as a (r×s×t) memory array.

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