Microprocessor and method for utilizing disparity between...

Details Microprocessor and method for utilizing disparity between... Microprocessor and method for utilizing disparity between...

2007-12-25

2007-12-25

Bataille, Pierre-Michel (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Shared memory area

C711S118000, C711S167000

Reexamination Certificate

active

11225865

ABSTRACT:
A microprocessor prioritizing cache line fill requests according to request type rather than issuing the requests in program order is disclosed. The requests are generated within the microprocessor at a core clock frequency, which is a multiple of the clock frequency of a bus coupling the microprocessor to a system memory from which the requests are satisfied. The request types are a blocking type and one or more non-blocking types. Blocking requests are initially assigned a higher priority than non-blocking requests. Once per bus clock, the highest priority request is selected for issuance on the bus, and the priority of each of the non-selected requests is increased. If more than one request is highest priority, the highest priority requests are selected in round-robin order. A request may have its priority changed if an event occurs which affects its type.

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