Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2007-10-09
2007-10-09
Kik, Phallaka (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C345S419000, C345S420000, C345S653000, C345S655000, C345S679000, C715S782000
Reexamination Certificate
active
10941233
ABSTRACT:
A method in accordance with the present invention prepares an alternate view of an integrated circuit (IC) layout from a top view thereof by selecting an initial polygon representing and IC feature from the top view of the layout, where the initial polygon is defined by a plurality of initial points. The coordinates the plurality of initial points are mapped onto coordinates of a plurality of translated points that define a second polygon representing an alternate view of the initial polygon. The mapping uses at least one of either the height of the initial polygon or the width of the initial polygon. The method can be used, for example and without limitation, to generate a three dimensional view from the top view of the layout or a sectional view of the layout.
REFERENCES:
patent: 5847967 (1998-12-01), Asao
patent: 7197372 (2007-03-01), Hazama
patent: 2004/0015804 (2004-01-01), Nakayama et al.
patent: 2004/0070582 (2004-04-01), Smith et al.
patent: 2004/0212612 (2004-10-01), Epstein et al.
patent: 2005/0134582 (2005-06-01), Hermann Claus et al.
patent: 2005/0154481 (2005-07-01), Berger et al.
patent: 2005/0168459 (2005-08-01), Baird
patent: 2005/0231505 (2005-10-01), Kaye et al.
patent: 2005/0248566 (2005-11-01), Vesely et al.
patent: 2005/0248580 (2005-11-01), Osako
patent: 2006/0010416 (2006-01-01), Keck et al.
patent: 2006/0192776 (2006-08-01), Nomura et al.
patent: 10049704 (1998-02-01), None
Yu et al., (“Layout-based 3D Solid Modeling for IC”, proceedings of International Symposium on VLSI Technology, and Applications, May 31, 1995, pp. 108-112).
Kidamdi et al., “Three-Dimensional Defect Sensitivity Modeling for Open Circuits in ULSI Structures”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 17, No. 4, Apr. 1998, pp. 366-371.
Chiang et al., “Challenges on Global Routing Correlation”, Proceedings of 4th International Conference on ASIC, Oct. 23, 2001, pp. 45-49.
Li et al., “Substrate Modeling and Lumpted Substrate Resistance Extraction for CMOS ESD/Latchup Circuit Simulation”, Proceedings of 36th Design Automation Conference, Jun. 21, 1999, pp. 549-554.
Altera Corporation
Kik Phallaka
Martine & Penilla & Gencarella LLP
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